In some conventional video processing systems that perform compression and/or decompression of digital video, one or more pictures (or frames or fields) of video are generally stored in memory such as dynamic random access memory (DRAM). Video data in DRAM is typically stored in a format that may be system and/or implementation dependent. Among other things, pictures stored in DRAM are utilized for motion-compensation prediction (MCP), which is also referred to as motion compensation (MC). Motion compensation involves reading many arrays of values from DRAM and processing data read from the DRAM in order to produce predicted sample values. These predicted values may be utilized during video decompression.
With the evolution of new digital video standards, video compression formats are continuously evolving. One of the most commonly utilized video formats is MPEG-2 (ISO/IEC 13818-2). A next generation offshoot of the MPEG-2 standard, which is likely to become widespread, is MPEG-4 AVC, also known as ITU H.264 (ISO/IEC 14496-10), and referred to as “AVC.” Decoding and encoding of AVC is much more demanding than MPEG-2 in terms of DRAM access performance, mainly because AVC uses motion compensation that is more complex than that used by MPEG-2. AVC is evolving with extensions proposed for 10 bit-per-pixel video samples (10-bit video) and 12 bit-per-pixel video samples (12-bit video) compared to the current standard of 8 bits-per-pixel (8-bit video). The use of 10-bit video increases DRAM performance requirements, partially because of the increased number of bits per pixel, and because of the inefficiency of packing 10 bits per sample into DRAM data words whose widths are generally powers of 2 (e.g., 16, 32, 64, 128). In other words, it may be more efficient to pack samples that are powers of two (2) into DRAM data words that it is to pack samples that are not powers of two (2).
Along with this trend towards increased demands on DRAM performance requirements, there is also a trend to integrate more functions on one chip, particularly in devices such as decoders that are utilized in high volume applications such as, cable and satellite set top boxes, and also digital television receivers and other broadband access devices. These highly integrated chips are often referred to as Systems-On-Chip (SOCs). Many of the functions combined on one chip, for example, the decoding of digital video, have real time requirements for DRAM performance.
As real time DRAM requirements increase, it becomes increasingly more difficult to design systems in which all real time demands are met by sharing access to DRAM. For instance, many successful designs use a unified memory architecture (UMA), in which one DRAM system supports DRAM access needs of all functions on a chip. In particular, extending the decoding performance of digital video decoding functions on large SOCs with UMA such that the video decoder may be expected to decode 10-bit digital video, leads to problems with DRAM real time performance.
In typical decoding systems, the real time performance of the DRAM subsystem tends to vary dynamically. The performance tends to vary in response to varying demands from the video decoding operations as well as other functions such as graphics, audio, and networking function, for example. A well-designed system is generally designed to operate reliably under instantaneous worst-case conditions. However, except for those worst-case conditions, normal operating conditions may not be as demanding as the instantaneous worst-case conditions.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.